The present invention relates to integrated circuits, and in particular, to contactless integrated circuits with a communication interface operating with electromagnetic induction and inductive coupling.
The present invention more particularly relates to the implementation of a wired logic function in an integrated circuit, allowing the processing of a selective identification request accompanied with a selection code.
FIG. 1 schematically shows a situation in which a selective identification request can be used. A data emitting-receiving station ST provided with an antenna coil and operating with inductive coupling emits a magnetic field FLD. A plurality of contactless integrated circuits CIC1, CIC2, . . . CICn (or transponders), also provided with antenna coils, are located in the emitting perimeter of the station, i.e., the interrogation field, for communicating with the station.
Each integrated circuit is identifiable by an identification code ID1, ID2, . . . IDn stored in an internal memory. Although not shown, each integrated circuit is arranged on a portable support to form a contactless operating device like a contactless chip card, an electronic tag, etc.
When the station ST wants to communicate with one of the integrated circuits, or inventory the integrated circuits present in the interrogation field, the station sends a selective identification request accompanied with a selection code. Each integrated circuit compares its ID code with the selection code, and sends back to the station an identification message comprising the ID code if the result of the comparison is positive.
The selection code sent by the station is generally of a smaller length than the ID code. Furthermore, the selective identification request may be accompanied with a parameter indicating the number N of bits to be compared between the two codes. The integrated circuits having an ID code identical to the selection code generally respond on a response scale comprising several response positions to avoid collisions between responses. These response positions may be random or depend on internal data of the integrated circuits.
By way of example, FIG. 2A shows the conventional format of a selective identification request as provided by the standard ISO/IEC/FCD 15693-3, called INVENTORY command, for allowing a data emitting-receiving station to inventory the contactless circuits present in its interrogation field. The INVENTORY command comprises a start of frame field SOF, a request flags field RF with a length of 8 bits, a command field CMD with a length of 8 bits (containing the INVENTORY command code), a mask length field ML with a length of 8 bits, a mask value field MV having a length from 0 to 8 bytes, a CRC code and a end of frame field EOF.
The term mask designates the selection code. Each integrated circuit compares its identification code ID to the mask MV supplied by the station. The number N of bits to be compared between the ID code and the mask MV is specified by field ML. Thus, as illustrated in FIG. 2B, an integrated circuit having an ID code of M bits, receiving a selective identification request comprising a field ML equal to N, only compares N bits of the ID code with N bits of the mask MV.
FIG. 2C shows the format of the response which is sent back by an integrated circuit having an ID code comprising N bits similar to mask MV. This response simply comprises the identification number ID of the integrated circuit preceded with the field SOF, and followed with a CRC code and with the end of frame field EOF.
To better understand the present discussion, FIG. 2D shows the response scale relating to an INVENTORY command. This response scale comprises various response positions TS0, TS1, . . . TSn, (Time Slots) on which the integrated circuits can position themselves. These response positions TS are controlled by the station and are determined by the sending of end of frame messages EOF, to which is added a response time t1.
The integrated circuits choose their response positions according to a number P, which is defined herein by the 4 bits of the ID code, which follow the N bits to be compared with the mask MV (16 possible response positions). A station can also force all the integrated circuits to respond on the first response position TSO by setting to 1 the bit 5 of field RF.
The processing of a selective identification request in a microprocessor integrated circuit presents generally no difficulty, and is performed by a program providing the comparison of the codes and the sending of the ID code if the result of the comparison is positive. The processing of a selective identification request in a wired logic integrated circuit is more delicate, and requires a relatively complex circuit occupying a non-negligible silicon surface area.
In view of the foregoing background, an object of the present invention is to provide a wired logic circuit with a relatively straightforward structure that is also compact for processing a selective identification request.
Another object of the present invention is to provide a wired logic circuit of the above mentioned type which is compatible with storage of the identification code of an integrated circuit in a serial output memory.
A serial output memory presents the advantage of having a relatively straightforward and low cost structure, since only one sense amplifier is required. Such a memory has a read time (bit after bit) which is rather long compared to the time given to respond to an identification request. If referred to the above cited standard, the minimal time t1 between the reception of the INVENTORY command and the first response position TS0 is on the order of 320 microseconds (FIG. 2D)
It is thus necessary to provide a first buffer register for storing mask MV, and a second buffer register for storing the identification code ID. The second buffer register allows the ID code to be rapidly emitted after its comparison with the selection code, and without the need of reading the serial memory a second time.
However, two buffer registers of several bytes each occupy a non-negligible place and do not fulfill the simplicity requirements of a wired logic circuit. Thus, still another object of the present invention is to provide a wired logic circuit capable of processing a selective identification request with a minimum number of buffer registers.
These and other objects, advantages and features according to the present invention are achieved by providing a method of processing, in an integrated circuit to which is allocated an identification code and a selective identification request accompanied with a selection code. The method comprises the steps of providing a shift register, a serial memory and a logic comparator, and storing the identification code of the integrated circuit in the serial memory, and loading the received selection code into the shift register.
The method further comprises coupling a serial output of the shift register to a first input of a logic comparator, and coupling a serial output of the memory to a second input of the comparator and to a serial input of the shift register. M shift pulses are applied to the shift register and M read pulses are applied to the memory. The comparator is inhibited when N shift and read pulses have been applied to the register and the memory. The method further includes delivering data present in the shift register to a communication interface of the integrated circuit, at a predetermined time, if the comparator delivers an equal signal.
The method may comprise a step of down-counting the number N using a first down-counter in which the number N is loaded, and a step of delivering an inhibit signal of the comparator when zero is reached. The comparator may be inhibited when the comparator delivers an inequality signal.
The step of delivering data present in the shift register to the communication interface preferably comprises the connection of an output of the shift register to the communication interface of the integrated circuit when an authorization signal is delivered. The authorization signal is delivered at the latest when the predetermined time is reached, except if the comparator delivers an inequality signal.
The authorization signal may be delivered by a second down-counter provided for counting a number P. The authorization signal is delivered when the down-counter reaches zero. A down-counting signal by one unit is applied to the second down-counter at each reception, by the integrated circuit, of a response request to the selective identification request.
The method preferably comprises a step of loading the number P into the second down-counter after the application of N shift pulses to the shift register and N read pulses to the memory, if the comparator does not deliver an inequality signal. The loading of the number P into the second down-counter comprises a bit by bit loading, into the second down-counter, of L bits of the identification code, delivered by the memory after the application of N read pulses.
The shift register may be designed with at least two shift registers arranged in parallel, and having serial inputs coupled to a demultiplexer and serial outputs coupled to a multiplexer. The method may be implemented for processing an INVENTORY command provided by the ISO/IEC/FCD 15693-3 standard.
The present invention also relates to an integrated circuit comprising an identification code of M bits and means for processing a selective identification request accompanied with a selection code. The processing means comprise a shift register comprising a serial output coupled to a first input of a logic comparator, a serial memory containing the identification code and comprising a serial output coupled to a second input of the comparator and to a serial input of the shift register.
The processing means further includes means for loading into the shift register a received selection code, means for applying M shift pulses to the shift register and M read pulses to the memory, means for inhibiting the comparator when N shift and read pulses have been applied to the register and the memory. There is also means for delivering to a communication interface of the integrated circuit, at a predetermined time, data present in the shift register, if the comparator delivers an equal signal.
The means for inhibiting the comparator may comprise a first counting circuit arranged to count the number N in synchronization with the shift and read pulses, and to deliver an inhibition signal of the comparator when the number N is counted. The first counting circuit may comprise a down-counter, means for loading the number N into the down-counter, and a logic circuit for delivering the inhibition signal when the down-counter reaches the value zero.
The means for inhibiting the comparator are arranged to inhibit the comparator when the comparator delivers an inequality signal. The means for inhibiting the comparator are also arranged to inhibit the first counting circuit when the comparator delivers an inequality signal. The comparator may comprise synchronous latches driven by a signal synchronized with the shift and read pulses. The means for inhibiting the comparator comprise a logic gate for blocking the synchronization signal of the comparator""s latches.
The means for delivering data present in the shift register to the communication interface of the integrated circuit comprise means for coupling a serial output of the shift register to the communication interface of the integrated circuit when an authorization signal is delivered, means for delivering the authorization signal at the latest when the predetermined time is reached, and means for preventing the delivery of the authorization signal when the output of the comparator presents an inequality value.
The means for delivering the authorization signal comprise a second counting circuit arranged to count a number P and to deliver the authorization signal when the number P is counted, and a controller for applying, to the counting circuit, a counting signal by one unit at each reception, by the integrated circuit, of a response request to the selective identification request. The second counting circuit may comprise a down-counter, means for loading the number P into the down-counter, and means for delivering the authorization signal when the down-counter reaches the value zero.
The means for loading the number P into the down-counter are arranged to start the loading of the number P after the application of N shift pulses to the shift register and N read pulses to the memory, if the comparator does not deliver an inequality signal. The means for loading the number P into the down-counter may comprise means for a bit by bit loading of L bits of the identification code delivered by the memory after N read pulses. The means for loading the L bits of the identification code into the down-counter may comprise a counter arranged to count L one bit loading cycles and means for inhibiting the loading of the down-counter when the number L is reached.
The shift register also comprises a parallel input for receiving the selection code. The shift register may comprise at least two shift registers arranged in parallel, having serial inputs coupled to a demultiplexer and serial outputs coupled to a multiplexer.
The integrated circuit preferably comprises a contactless communication interface operating with inductive coupling. The integrated circuit is arranged to process a selective identification request INVENTORY provided by the ISO/IEC/FCD 15693-3 standard. The present invention also relates to a portable electronic device of the chip card type, electronic label type or analog type, with each comprising an integrated circuit according to the invention.